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february 2010 doc id 17160 rev 1 1/23 23 SPMD150STP 1.5 a stepper motor driver module features wide supply voltage range, up to 42 v 1.5 a output average working current full/half step and micro-stepping drive capability logic signals ttl/cmos compatible programmable motor phase current selectable slow/fast current decay non dissipative overcurrent protection remote shutdown thermal shutdown module size: 50.8 x 50.8 x 14.7 mm operating temperature range -40c to 85 c description the SPMD150STP is a highly integrated stepper motor driver module, that al lows the user to easily design a complete motor control system for two- phase bipolar stepper motors, interfacing directly the microprocessor to the motor. the SPMD150STP is an easy-to-use fully integrated answer to motion control issues. the phase current is chopper controlled, allowing good performances and high speed. modules offer an extensive range of protection such as overcurrent and thermal shut-down, that make it ?bullet? proof as required in modern motion control systems. metallic case allows mo dule to operate without external heat-sink or ventilation; moreover the sealed and molded package offers a complete protection against harsh environments. table 1. device summary order code SPMD150STP www.st.com
contents SPMD150STP 2/23 doc id 17160 rev 1 contents 1 block diagram and pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 function description and appl ication information . . . . . . . . . . . . . . . . 11 4.1 power stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 logic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 pwm current controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5 stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5.1 half step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5.2 normal drive mode (full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . 17 4.5.3 wave drive mode (full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . 17 4.5.4 microstepping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.7 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.8 case grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
SPMD150STP block diagram and pin connection doc id 17160 rev 1 3/23 1 block diagram and pin connection figure 1. block diagram figure 2. connection diagram (top view)
block diagram and pin connection SPMD150STP 4/23 doc id 17160 rev 1 table 2. pin description pin n. name function 1 vss logic stage supply voltage. this pin mu st be supplied with 3.3v or 5v source. 2ref voltage reference output. a voltage of 1.225v is available at this pin. it can be used to set the output current level. 3 reset reset pin. a logic level low restores the home state (state 1) on the phase sequence generator. a 10k ? pull-up resistor is internally connected to vss. 4clock step clock. on the rising edge of this signal, the phase sequence generator changes its state position, consequently the motor performs a step. a 10k ? pull-up resistor is internally connected to vss. 5 cw/ccw spin direction control input. a logic level high sets clockwise motor rotation. a logic level low sets counter clockwis e motor rotation.ph ysical direction of rotation depends on windings connection also. a 10 k ? pull-up resistor is internally connected to vss. 6vrefa phase a/b current setting input. connect this pin to a properly scaled ref (pin2) voltage, to fix the maximum phase output current. connecting a variable voltage source (i.e. microcontroller dac), it is possible to perform micro- stepping drive. the pin is internally connected to a 100k pull-down resistor, with a 470pf parallel capacitor. 7 rca phase a/b current controller off-time set pin. use this pin to set the desired off-time of the switching current controller. a 470pf capacitor and 56k resistor are internally connected between this pin and gnd1 (pin13), giving a 16 s -time. 8en module enable input. a high logic level enables module operation. en (pin8) must be low, during power-up and power-down sequence, high during normal operation. (when this input is low, the output phases are in high impedance state, enabling the manual positioning of the motor). a 100k ? pull-up resistor is internally connected to vss. a 100nf capacitor is internally connected to gnd1 9control phase current decay mode selection input. a logic level high sets the slow decay mode. a logic level low sets the fast decay mode a 10k ? pull-up resistor is internally connected to vss. 10 half/full half/full step mode selection input. a logic level high sets the half step mode. a logic level low sets the full step mode. a 10k ? pull-up resistor is internally connected to vss. 11 vrefb phase c/d current setting input. connect this pin to a properly scaled ref (pin2) voltage, to fix the maximum phase output current. connecting a variable voltage source (i.e. microcontroller dac), it is possible to perform micro-stepping drive. the pin is internally connected to a 100k pull-down resistor, with a 470pf parallel capacitor.
SPMD150STP block diagram and pin connection doc id 17160 rev 1 5/23 12 rcb phase c/d current controller -time set pin. use this pin to set the desired off-time of the switching current controller. a 470pf capacitor and 56k ? resistor are internally connected between this pin and gnd1 (pin13), giving a 16 s -time. 13 gnd1 logic stage gnd. return path for th e logic signals and vss (pin1) supply voltage. 14 gnd2 power stage gnd. return path for the power stage and vs (pin19) supply voltage. 15 phd phase d output 16 phc phase c output 17 phb phase b output 18 pha phase a output 19 vs power stage supply voltage. module and motor supply voltage. maximum voltage must not exceed the specified values. table 2. pin description (continued) pin n. name function
maximum ratings SPMD150STP 6/23 doc id 17160 rev 1 2 maximum ratings table 3. absolute maximum ratings symbol parameter value unit v s dc supply voltage (pin19) 50 v v ss dc logic supply voltage (pin1) 7 v v input voltage range at pins vrefa, vrefb, rca, rcb, en, clock, cw/ccw , half/full , control -0.3 to 7 v io-pk output peak current 2.5 a t stg storage temperature range ? 40 to +105 c t op operating case temperature range ? 40 to +85 c
SPMD150STP electrical characteristics doc id 17160 rev 1 7/23 3 electrical characteristics t a = 25 c and v s = 24 v, v ss = 5 v unless otherwise specified. table 4. electrical characteristics symbol parameter test conditions value unit min typ max power stage v s dc supply voltage 10 42 v i s quiescent supply current (pin19) all bridges 5 10 ma v sth(on) turn-on input threshold 6.6 7 7.4 v v sth(off) turn-off input th reshold 5.6 6 6.4 v v vs-ph output voltage drop (vs to pins 15,16,17,18) io = -1.5a 0.9 v v ph-gnd output voltage drop (pins15,16,17,18 to gnd2) io = 1.5a 1.1 v io phase average working current 1.5 a protections block io-sc phase short circuit current internally limited by overcurrent protection ( figure 7 ) 45.67.1 a t ocd(on) overcurrent detection turn-on delay time ( figure 7 )200ns t ocd(off) overcurrent detection turn-off delay time ( figure 7 )100ns t j(off) junction shutdown temperature 165 c logic interface v ss dc logic supply voltage 3.0 5 5.25 v i ss quiescent supply current (pin 1) all inputs open 1.2 ma v il low level input voltage pin 5,9,10 v ss = 3 to 5.25v -0.3 0.8 v v ih high level input voltage pin 5,9,10 v ss =3 to 5.25v 2vssv v th(on) turn-on input threshold pin 3,4,8 v ss =3 to 5.25v ( figure 1 , 2 , 3 , 4 ) 1.8 2.0 v v th(off) turn-off input threshold pin 3,4,8 v ss =3 to 5.25v ( figure 1 , 2 , 3 , 4 ) 0.8 1.3 v v th(hys) input threshold hysteresis pin 3,4,8 v ss =3 to 5.25v ( figure 1 , 2 , 3 , 4 ) 0.25 0.5 v i il low level input current pin 3,4,5,8,9,10 -0.5 ma
electrical characteristics SPMD150STP 8/23 doc id 17160 rev 1 i ih high level input current pin 3,4,5,8,9,10 10 ua v ref reference output voltage (pin 2) 1.21 1.225 1.24 v ref_res reference output resistance (pin2) 10 k vrefx_res current setting input resistance (pin 6,11) 100 k timing definition t d(on)en enable to output turn-on delay io=2.5a, resistive load ( figure 3 ) 100 250 400 ns t d(off)en enable to output turn-off delay io=2.5a, resistive load ( figure 3 ) 300 550 800 ns t rise output rise time io=2.5a, resistive load ( figure 3 ) 40 250 ns t fall output fall time io=2.5a, resistive load ( figure 3 ) 40 250 ns t dclk clock to output delay time io=2.5a, resistive load ( figure 4 ) 2s t clk(min)l clock minimum low level time ( figure 5 )1s t clk(min)h clock minimum high level time ( figure 5 )1s f clk clock frequency 50 khz t s(min) minimum set-up time ( figure 6 )1s t h(min) minimum hold time ( figure 6 )1s t r(min) minimum reset time ( figure 6 )1s t rclk(min) minimum reset to clock delay time ( figure 6 )1s table 4. electrical characteristics (continued) symbol parameter test conditions value unit min typ max
SPMD150STP electrical characteristics doc id 17160 rev 1 9/23 figure 3. switching char acteristic definition figure 4. clock to output delay time figure 5. minimum timi ng definition: clock 9 wk21 9 wk2)) (1 , 287 w w w )$// w '2))(1 w 5,6( w '21(1 ',1 &/2&. , 287 w w w '&/. 9 wk21 ',1 &/2&. w &/.0,1+ w &/.0,1/ 9 wk2)) 9 wk21 ',1 9 wk2))
electrical characteristics SPMD150STP 10/23 doc id 17160 rev 1 figure 6. minimum timing definition: logic inputs figure 7. overcurrent de tection timing definition &/2&. 5(6(7 w 60,1 w +0,1 w 50,1 w 5&/.0,1 /2*,&,13876 ',1 9 wk2)) 9 wk21 9 wk21 , 629(5 , 287 9 (1 w 2&'2)) w 2&'21 ',1 21 2)) %5,'*(
SPMD150STP function description and application information doc id 17160 rev 1 11/23 4 function description and application information SPMD150STP can be seen divided in several main blocks (see figure 1 ): power stage, to drive the motor windings logic interface, to interface the external signals to the internal circuitry pwm current controller, to fix and control the current flowing in the motor phase windings decay control block, to contro l the phase current decay mode phase sequence generator, to generate the motor phases driving sequence protection block, performing over current protectionand thermal shut-down to protect the power bridges 4.1 power stage stmd150stp integrates two independent mosfet full bridges, with intrinsic fast freewheeling diodes. switching patterns are generated by the phase sequence generator and by the pwm current controller. the power mosfet cross conduction in one bridge leg, is avoided introducing a dead time (t dt = 1 s typical), between fets switch off and the switch on. vs (pin19) and gnd2 (pin14) must be connecte d to the supply voltage, which can range from 10 v to 42 v. 4.2 logic interface logic interface connects the external logic signal to the proper internal blocks. reset (pin3), clock (pin4), cw/ccw (pin5), control (pin9) and half/full (pin10) have a 10k pull-up resistor to vss (pin1), in order to prevent floating pins; vss can be connected to 3.3 v or 5 v, a llowing the interface wit h the most popular microcontroller. the internal structure is shown in figure 8 . en (pin8) has identical input structure, with the exception that the mosfet drain of the over-current and thermal protection is also connected to this pin (see figure 9 ). due to this connection some care needs to be taken in driving this pin. inside the module a 100 k resistor and a 100 nf capacitor is provided, an open collector driving is therefore the suggested solution.
function description and application information SPMD150STP 12/23 doc id 17160 rev 1 figure 8. logic inputs internal structure figure 9. en pin open collector driving 4.3 pwm current controller the control block is composed by a constant off-time pwm current controller for both two bridges. the current control circuit senses t he bridge current, by sensing the voltage drop across a sense resistor connected between the source of the two lower power mosfets and ground. as the current in the motor buildup, the voltage across the sense resistor increases proportionally. when the voltage on the sense resistor becomes greater than the voltage at the reference inputs vrefa (pin6) or vrefb (pin11), the sense comparator triggers a mono-stable circuit, switching the bridge off. the bridge mosfets remain off for the time set by pin rca (pin7) or rcb (pin12); during this off-time (see figure 11 , toff versus roff and coff), the motor phase current re- circulates as defined by the selected decay mode, described in the next section. when the mono-stable circuit times out, th e bridge will turn on again. si nce the internal dead time t dt , used to prevent cross conduction in the bridge, delays the turn on of the power mosfets, the effective off-time is the sum of the mono-stable time plus the t dt (1s). to set the toff relative to bridge a, it is necessary to connect a proper resistor ra and/or a proper capacitor ca in parallel between pin rca and gnd1, see figure 10 and figure 11 ; to set the toff relative to bridge b, it is necessary to connect a proper resistor rb and/or a proper capacitor cb in parallel between pin rcb and gnd1, see figure 10 and figure 11 ; a 56 k resistor and a 470 pf capacitor are already present between pin rca/b and gnd1 inside the
SPMD150STP function description and application information doc id 17160 rev 1 13/23 module, fixing a typical 16 s off time for both bridges. the toff value can be modified adding a capacitor to gnd1, increasing the off time, or adding a resistor to gnd1 decreasing the off-time. figure 10. toff setting circuit roff = ra // 56k [k ], coff = ca + 470pf [pf] figure 11. toff versus roff and coff to set the maximum motor phase current it is necessary to give the proper reference voltage at input vrefa (pin6) and vrefb (pin11). the relationship between the voltage at vrefx pin and the phase current i outx is the following: i outx = vrefx / 0.192 [a] an internal 100 k resistor and a 470 pf capacitor are connected in parallel between vrefx and gnd1 (see figure 12 ).
function description and application information SPMD150STP 14/23 doc id 17160 rev 1 figure 12. vrefa and vrefb internal connection the voltage at vrefa and vrefb can be supplied in two way: using an external source (see figure 13 ), driving vrefa and vrefb pins together or separately as in the micro-stepping mode (i.e: a micro-controller fixes a variable voltage to get variable current in the stepper motor phases). figure 13. vrefx from an external source using the module reference voltage source, ref (pin2) (see figure 14 ), which supplies 1.225 v. the ref pin has a 10 k resistor in series, take that in account during design. in this case a proper resistor rx must be connected between ref and gnd1, vrefa and vrefb will be connected t ogether to ref pin (see figure 14 ). use following equation to calculate rx: rx = (500 x i outx ) / [319 - (60 x i outx )] [k ] where i outx = [a]
SPMD150STP function description and application information doc id 17160 rev 1 15/23 figure 14. vrefx from internal source 4.4 decay modes the control input is used to select the behavior of the bridge during the off time. when the control pin is low, the fast decay mode is selected and both transistors in the bridge are switched off during the off time. when the control pin is high, the slow decay mode is selected and only the low side transistor of the bridge is switched off during the off time. figure 15 shows the operation of the bridge in the fast decay mode. at the start of the off time, both of the power mosfets are switched off and the current recirculates through the two opposite free wheeling diodes. the current decays with a high di/dt, since the voltage across the coil is essentially the power supply voltage. after the dead time, the lower power mosfet in parallel with the conducting diode is turned on in synchronous rectification mode. in applications where the motor current is low it is possible that the current can decay completely to zero during the off time. at this point if both of the power mos were operating in the synchronous rectification mode it would then be possible for the current to build in the opposite direction. to prevent this only the lower power mos is operated in synchronous rectification mode. this operation is called q uasi-synchronous rectification mode. when the mono-stable circuit times out, the power fets are turned on again after some delay set by the dead time to prevent cross conduction.
function description and application information SPMD150STP 16/23 doc id 17160 rev 1 figure 15. fast decay mode output stage configurations figure 16 shows the operation of the bridge in the slow decay mode. at the start of the off- time, the lower power fet is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slowly. after the dead time the upper power fet is operated in the synchronous rectification mode. when the mono-stable circuit times out, the lower power fet is turned on again after some delay set by the dead time to prevent cross conduction. figure 16. slow decay mode output stage configurations 4.5 stepping sequence generation the phase sequence generator is a state machine that provides the phase and the enable inputs for the two bridges to drive a stepper motor in either full step or half step. two full step modes are possible, the normal drive mode where both phases are energized each step and the wave drive mode where only one phase is energized at a time. the drive mode is selected by the half/full input and the current state of the sequence generator as described below. a rising edge of the clock input advances the state machine to the next state. the direction of rotation is set by the cw/ccw input. the reset input resets the state machine to home state. 4.5.1 half step mode a logic level high on the half/full input selects half step mode. figure 17 shows the motor current waveforms and the state diagram for the phase sequencer generator. at start- up or after a reset the phase se quencer is at state 1, home state. after each clock pulse the state changes following the sequence 1,2,3,4,5,6,7,8,? if cw/ ccw is high (clockwise movement) or 1,8,7,6,5,4,3,2,? if cw/ccw is low (counterclockwise movement). % ( 0 , 7 1 2 $ m v'($'7,0( &48$6,6<1&+521286 5(&7,),&$7,21 ' m v6/2:'(&$< ',1 % ( 0 , 7 1 2 $ m v'($'7,0( &6<1&+521286 5(&7,),&$7,21 ' m v'($'7,0( ',1
SPMD150STP function description and application information doc id 17160 rev 1 17/23 figure 17. half step mode 4.5.2 normal drive mode (full-step two-phase-on) a low level on the half/full input selects the full step mode. if the low level is applied when the state ma1chine is at an odd numbered state, the normal drive mode is selected. figure 18 shows the motor current waveform state diagram for the state machine of the phase sequencer generator. the normal drive mode can be selected easily, by holding the half/full input low and applying a reset. at start -up or after a reset the state ma chine is in state1. after the half/full input is kept low, state changes following the sequence 1,3,5,7,? if cw/ccw is high (clockwise movement) or 1,7,5,3,? if cw/ccw is low (counterclockwise movement). figure 18. normal drive mode 4.5.3 wave drive mode (full-step one-phase-on) a low level on the pin half/full input selects the full step mode. if the low level is applied when the state machine is at an even numbered state, the wave drive mode is selected. figure 19 shows the motor current waveform and the state diagram for the state machine of the phase sequence generator. to enter the wave drive mode the state machine must be in an even numbered state. an example of selecting the wave drive mode is the following: to apply a reset first; keeping the half/full input high, to apply one pulse to the clock input; then, to apply the logic level low to the half/full input. this sequence first forces the state machine to sate 1. ',1 , 287$ , 287% &/2&. 6wduw8sru5hvhw ',1 , 287$ , 287% &/2&. 6wduw8sru5hvhw
function description and application information SPMD150STP 18/23 doc id 17160 rev 1 the clock pulse, with the half/full input high, advances the state machine from state 1 to either state 2 or 8 depending on the cw/ccw input. starting from this point, keeping the half/full input low, the state machine will advance following the sequence 2,4,6,8,? if cw/ccw is high (clockwise movement) or 8,6,4,2,? if cw/ ccw is low (counterclockwise movement). figure 19. wave drive mode 4.5.4 microstepping stmd150stp has two separate control current loop, with the possibilit y to set the current level in an independent way (by means vrefa and vrefb); this feature make possible the actuation of the micro-stepping mode. micro-stepping mode is a full step mode performed with a not fixed current in the motor phases, but with a current varying in a sinusoidal mode; that means the current flowing in the motor is not a square wave, but a sinusoidal wave. main commands remain the same, but during the period of each clock step, vrefa and vrefb are incremented or decremented through a defined number of level, this number gives the name to the micro-stepping granularity; as example, a 64 micro-step per step means that, for each ?standard? step there are 64 step values on vrefa/b (from zero to vrefa/b max and from vrefb/a max to zero, see figure 20 ) ',1 , 287$ , 287% &/2&. 6wduw8sru5hvhw
SPMD150STP function description and application information doc id 17160 rev 1 19/23 figure 20. microstepping 4.6 non-dissipative overcurrent protection the SPMD150STP integrates an overcurrent protection circuit. this circuit provides protection against a short circuit to ground or between two phases of the bridge. to implement the over current detection, a sensing element that delivers a small but precise fraction of the output current is implemented with each high side power mosfet. since this current is a small fraction of the output current, there is very little additional power dissipation. this current is compared with an internal reference, when the output current reaches the detection threshold (typically 5.6a) the ocp comparator signals a fault condition. if a fault condition is detected, the en pin is pulled below the turn off threshold (1.3v typical) by an internal open drain mosfet with a pull down c apability of 4ma.
function description and application information SPMD150STP 20/23 doc id 17160 rev 1 an internal100 k resistor plus a 100 nf capacitor connected to the en pin, seta 400 s off time, before recovering normal operation (see figure 9 and figure 21 ). figure 21. overcurrent protection waveforms 4.7 thermal characteristics the case-to-ambient thermal resistance is 8 c/w. this produces a 40 c temperature increase of the module surface for 5 w of internal dissipation. according to ambient temperature and/or to maximum case operating temperature (85 c), an additional heat sink or forced ventilation may be required. 4.8 case grounding the module case is internally connected to gnd1 (pin13) and gnd2 (pin14). to obtain additional effective emi shield, the pcb area below the module can be used as an effective sixth side shield.
SPMD150STP package mechanical data doc id 17160 rev 1 21/23 5 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 22. package dimensions
revision history SPMD150STP 22/23 doc id 17160 rev 1 6 revision history table 5. document revision history date revision changes 22-feb-2010 1 first release
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